`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    11:05:50 07/06/2014 
// Design Name: 
// Module Name:    mod_7_6bit 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module mod_11_6bit(
    input [5:0] in,
	 output reg [3:0] out
    );

always@(in)
case(in)
0: out = 4'd0;
1: out = 4'd1;
2: out = 4'd2;
3: out = 4'd3;
4: out = 4'd4;
5: out = 4'd5;
6: out = 4'd6;
7: out = 4'd7;
8: out = 4'd8;
9: out = 4'd9;
10: out = 4'd10;
11: out = 4'd0;
12: out = 4'd1;
13: out = 4'd2;
14: out = 4'd3;
15: out = 4'd4;
16: out = 4'd5;
17: out = 4'd6;
18: out = 4'd7;
19: out = 4'd8;
20: out = 4'd9;
21: out = 4'd10;
22: out = 4'd0;
23: out = 4'd1;
24: out = 4'd2;
25: out = 4'd3;
26: out = 4'd4;
27: out = 4'd5;
28: out = 4'd6;
29: out = 4'd7;
30: out = 4'd8;
31: out = 4'd9;
32: out = 4'd10;
33: out = 4'd0;
34: out = 4'd1;
35: out = 4'd2;
36: out = 4'd3;
37: out = 4'd4;
38: out = 4'd5;
39: out = 4'd6;
40: out = 4'd7;
41: out = 4'd8;
42: out = 4'd9;
43: out = 4'd10;
44: out = 4'd0;
45: out = 4'd1;
46: out = 4'd2;
47: out = 4'd3;
48: out = 4'd4;
49: out = 4'd5;
50: out = 4'd6;
51: out = 4'd7;
52: out = 4'd8;
53: out = 4'd9;
54: out = 4'd10;
55: out = 4'd0;
56: out = 4'd1;
57: out = 4'd2;
58: out = 4'd3;
59: out = 4'd4;
60: out = 4'd5;
61: out = 4'd6;
62: out = 4'd7;
63: out = 4'd8;
endcase

endmodule
